a) Field of the Invention
The present invention relates to a method of fabricating a semiconductor device, and more particularly to a method of fabricating a multi power source semiconductor device handling multi-level voltages.
b) Description of the Related Art
Semiconductor elements in a semiconductor integrated circuit device are miniaturized due to highly concentrated integration. A driving voltage of a semiconductor integrated circuit has a tendency to be lowered in order to save electric power and to establish such an electric field in the miniaturized element that is not excessively high. For example, an analogue circuit such as transistor-transistor logic (TTL) has been developed by 5 V power source. However, a digital circuit developed later is commonly driven by 3.3 V power source. The driving power source for the digital circuit has a tendency to be further decreased to 2.5 V. In a memory device or another device, further lowering of the driving voltage is performed.
Sometimes it is required to handle multi-level voltages on an integrated circuit device containing several kinds of functional circuits. Such a semiconductor device is named as multi power source semiconductor device in the present specification. The multi power source semiconductor device comprises a high voltage circuit driven by a power source of comparatively high voltage and a low voltage circuit driven by a power source of comparatively low voltage.
For example, in an n-type metal-oxide-semiconductor (MOS) transistor, the source electrode is commonly grounded or earthed and the earth potential and the source voltage are selectively applied to the drain electrode and the gate electrode. It is required that the gate oxide layer has a dielectric breakdown voltage higher than the source voltage and that the insulating property doesn't show aging by application of the voltages. Furthermore, it is required that a breakdown voltage between the drain and the source electrodes is higher than the source voltage and that the properties of the element do not show aging. In a multi power source device, the low voltage circuit and the high voltage circuit are different in the level of the voltage applied to a transistor.
In some kinds of multi power source semiconductor devices, a distance between the drain and the source regions in a MOS transistor for low voltage circuit is made to be different from that in a MOS transistor for high voltage circuit. The distance between the drain and the source regions of a transistor is commonly determined from the length of the gate electrode (gate length) so that the gate length is short in a MOS transistor for low voltage circuit and long in that for high voltage circuit. Hence, it is capable of providing an efficient MOS transistor applicable to both low voltage and high voltage circuits by varying the gate length corresponding to the source voltages. Formation of transistors with various gate lengths is easy as it is a planar-pattern problem.
In some kinds of multi power source devices, the thickness of the oxide layer of a MOS transistor for low voltage circuit is made to be different from that of a MOS transistor for high voltage circuit. The MOS transistor for low voltage circuit has a thin gate oxide layer and that for high voltage circuit has a thick gate oxide layer. Hence, it is capable of providing an efficient MOS transistor applicable to both low voltage and high voltage circuits by varying the thickness of the gate oxide layer corresponding to the source voltage. However, in order to form the gate oxide layers different in thickness, the number of steps for forming the gate oxide layers is required to be more than two.
An example of fabricating a multi power source complementary MOS (CMOS) semiconductor device with gate oxide layers having different thicknesses will be described referring to FIGS. 2A to 2F.
For example, in the surface region of a p-type semiconductor substrate 101, p-type wells 102p and 104p and n-type wells 102n and 104n are formed and a field oxide layer 105 is formed to confine active regions on the substrate surface as shown in FIG. 2A. The p-type well 102p and the n-type well 102n are the regions for forming for example, CMOS transistors of low voltage circuit of 3 V and the p-type well 104p and the n-type well 104n are the regions for forming for example, CMOS transistors of high voltage circuit of 5 V.
On the surface of each active region confined by the field oxide layer 105, the first gate oxide layer 106 of about 12 nm thick is formed.
As shown in FIG. 2B, a resist mask R1 having a window on the low voltage circuit region is formed on the semiconductor substrate. The gate oxide layer 106 exposed in the window on the surface of the active region is removed by etching using the resist mask R1. At the same time, the field oxide layer 105 exposed to the window is also etched. However, most of the field oxide layer remains because of its thickness of more than 300 nm. The resist mask R1 is removed after removing the gate oxide layer in the low voltage circuit region.
As shown in FIG. 2C, the semiconductor substrate surface is further oxidized thermally to form the second gate oxide layer 107 of about 9 nm thick on the active region in the low voltage circuit region. Simultaneously, thermal oxidization of the active region in the high voltage circuit region also proceeds to change the first gate oxide layer 106 of 12 nm thick into the third gate oxide layer 108 of about 14 nm thick.
After the second gate oxidation, boron (B) ions are implanted into the entire exposed surface of the substrate at an accelerating energy of 15 keV at a dose of 6.0.times.10.sup.11 cm.sup.-2. By the ion implantation, a threshold voltage of the p-type well 104p is controlled.
As shown in FIG. 2D, a resist mask R2 having a window on the p-type well 102p is formed on the surface of a semiconductor substrate. A threshold voltage of the p-type well 102p is controlled by implanting boron ions at an accelerating energy of 15 keV at a dose of 6.0.times.10.sup.11 cm.sup.-2, by use of the resist mask R2. After the ion implantation, the resist mask R2 is removed.
As shown in FIG. 2E, a resist mask R3 having a window on the n-type well 102n is newly formed on the semiconductor substrate. Using the resist mask R3, boron ions are implanted at an accelerating energy of 15 keV at a dose of 2.2.times.10.sup.12 cm.sup.-2. By the ion implantation, a threshold voltage of the n-type well 120n is controlled. After the ion implantation, the resist mask R3 is removed.
As shown in FIG. 2F, a resist mask R4 having a window on the n-type well 104n is formed on the substrate surface. Using the resist mask R4, boron ions are implanted at an accelerating energy of 15 keV at a dose of 2.5.times.10.sup.12 cm.sup.-2. By the ion implantation, the threshold voltage of the n-type well 104n is controlled.
By these four ion implantations, boron ions are implanted into the p-type well 102p, the n-type well 102n, the p-type well 104p, and the n-type well 104n at the doses of 1.2.times.10.sup.12 cm.sup.-2, 2.8.times.10.sup.12 cm.sup.-2, 6.0.times.10.sup.11 cm.sup.-2 and 3.1.times.10.sup.12 cm.sup.-2, respectively. Thus, channel dopings to each of the CMOS transistors for low and high voltage circuits are performed so that the threshold voltage of each transistor is controlled.
In FIG. 2C, ions are implanted into the entire surface of substrate at a dose fitting to the lowest value of channel doping so that four kinds of dose can be realized using only three masks in the three steps shown in FIGS. 2D, 2E, and 2F. However, in order to form the gate oxide layers having different thicknesses, the resist mask R1 is used in FIG. 2B so that the total number of masks in the steps shown in FIGS. 2A to 2F amounts to four.
As described above, in fabricating a multi power source CMOS semiconductor device, four masks were needed to realize formation of the gate oxide layers with two kinds of thickness and to realize four kinds of channel doping. In process of fabricating a semiconductor device, the number of masks has a significant influence on the production cost and on the fabrication efficiency. It is desirable to decrease the number of masks as less as possible in order to decrease the production cost and to increase the fabrication efficiency.